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The concept describes an efficient implementation of an IEEE 754 single precision floating point multiplier using reversible logic targeted for Xilinx Virtex-4 FPGA. Reversible logic is used to reduce the power dissipation as compared to classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Peres gate is one of the simple reversible logic gate and its quantum cost is 4. Because of its simplicity as well as lowest quantum cost, Peres gate is used to design entire single precision floating point multiplier circuit. Verilog is used to implement a technology-independent pipelined design. The proposed design can be made to handle overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. Rounding may also be implemented by truncation method for further reduction in power and area. The entire design is modeled using Verilog hardware description language .The coding is done on Xilinx ISE 12.2 and simulation is performed on Modelsim 6.3.